Multiple power source-semiconductor integrated circuit

ABSTRACT

In a multiple power source semiconductor integrated circuit that is manufactured using a process which generates a large leakage current, supply of power to a function block that is not being used is stopped to reduce unnecessary power consumption. A multiple power source semiconductor integrated circuit ( 1 ) includes first to fourth function blocks ( 11 ) to ( 14 ) that are supplied with power from first to fourth power supply circuits ( 3 ) to ( 6 ), respectively, and a power supply control circuit ( 40 ) that controls supply of power by the first to fourth power supply circuits ( 3 ) to ( 6 ) under the control of a microcomputer as the first function block ( 11 ). The power supply control circuit ( 40 ) halts the supply of power to the first to fourth function blocks ( 11 ) to ( 14 ) when receiving prescribed data from the first function block ( 11 ), and restarts the supply of power when receiving a first or second interrupt signal ( 55 ) or ( 56 ) from outside.

TECHNICAL FIELD

The present invention relates to power saving of a multiple power sourcesemiconductor integrated circuit and, more particularly, to power supplycontrol of a multiple power source semiconductor integrated circuit inwhich plural function blocks are packaged.

BACKGROUND ART

Recently, portable electronic devices such as portable compact discplayers (hereinafter, referred to as CD players) or portable minidiscplayers have become widespread. Such electronic device includes, in manycases, a signal processing LSI which is a semiconductor integratedcircuit for implementing characteristic functions of the device, forexample, reading data from a compact disc and converting the same intoan audio signal to output the same, and a microcomputer which is ageneral-purpose semiconductor integrated circuit for controlling thesignal processing LSI.

The following summarizes characteristics of the signal processing LSIand the microcomputer.

It is required that power consumption of the signal processing LSIduring operation should be small, because when the signal processing LSIis driven by batteries, the operating time (audio reproduction time inthe case of CD players) per battery becomes longer as the powerconsumption during the operation gets smaller. Thus, the signalprocessing LSI is manufactured using a Low-Vt process (Vt is anabbreviate of a threshold voltage) which can lower the operatingvoltage. Since the Low-Vt process is a process that can lower theoperating voltage but increases a leakage current, some measures aretaken by powering off the signal processing LSI using the Low-Vt processwhen not used, thereby to suppress the leakage current and reduce thebattery consumption. In addition, the signal processing LSI is amultiple power source semiconductor integrated circuit in which adriving voltage of an interface circuit for peripheral circuits (highvoltage driving) and a driving voltage of an internal circuit (lowvoltage driving) are different from each other, and it reduces the powerconsumption during the operation by minimizing the driving voltage ofthe internal circuit.

On the other hand, the microcomputer is commonly used constantly beingpowered on, because it must accept instructions for the electronicdevices from the user. Accordingly, the microcomputer is manufactured byusing a High-Vt process in which the leakage current is small.

Further, as the portable electronic devices are further miniaturized,the efforts to package plural function blocks into one semiconductorintegrated circuit have been made. In many cases, the respectivefunction blocks need different driving voltages. Accordingly, byintegrating the plural function blocks which need the different drivingvoltages into one semiconductor integrated circuit, the number of powersources for the semiconductor integrated circuit is further increased.

FIG. 13 is a block diagram illustrating a conventional multiple powersource semiconductor integrated circuit, and power supply circuits forthe multiple power source semiconductor integrated circuit. In thisfigure, reference numeral 1 g denotes a multiple power sourcesemiconductor integrated circuit, and numeral 2 denotes a main powersource, numerals 3 to 7 denote first to fifth power supply circuits eachincluding a DC/DC converter that supplies an arbitrary power supplyvoltage, and a power supply switch. Reference characters VDD1 to VDD5denote arbitrary power supply voltages. Numerals 11 to 14 denote firstto fourth function blocks that are included in the multiple power sourcesemiconductor integrated circuit 1 g, numeral 15 denotes an input/outputterminal circuit of the multiple power source semiconductor integratedcircuit 1 g, numerals 21 to 25 denote external power supply terminalsthat receive the corresponding power supply voltages VDD1 to VDD5 whichare supplied to the multiple power source semiconductor integratedcircuit 1 g, and numerals 31 to 35 denote internal power supply lines ofthe multiple power source integrated circuit 1 g.

FIG. 13 shows an example in which the first function block 11 is amicrocomputer for controlling the system, the second function block 12is a signal processing circuit, the third function block 13 is anearthquake-resistant storage circuit, and the fourth function block 14is an analog circuit. Further, the respective power supply switchesincluded in the power supply circuits 3 to 7 are always ON, and alwayssupply power.

Next, the operation of the conventional multiple power sourcesemiconductor integrated circuit 1 g that is constructed as describedabove will be described.

When the main power source 2 is turned on, the power supply circuits 3to 7 transform a power supply voltage which is supplied from the mainpower source 2 into arbitrary power supply voltages VDD1 to VDD5, andsupply these voltages to the multiple power source semiconductorintegrated circuit 1 g. The multiple power source semiconductorintegrated circuit 1 g receives the power supply voltages VDD1 to VDD5which are supplied from the power supply circuits 3 to 7 through thecorresponding external power supply terminals 21 to 25. The power whichis received through the external power supply terminals 21 to 25 issupplied to the function blocks 11 to 14 and the input terminal circuit15 via the internal power supply lines 31 to 35. The respective functionblocks 11 to 14 and the input/output terminal circuit 15 executerespective processing for implementing prescribed functions.

Here, the power supply circuits 3 to 7 constantly supply power to therespective function blocks 11 to 15 through the corresponding externalpower supply terminals 21 to 25, and the power is continuously suppliedeven when the function blocks 11 to 14 are not used.

Since the conventional multiple power source semiconductor integratedcircuit is constructed as described above, the respective functionblocks are always powered on, regardless of whether the function blocksare used or not. Conventionally, unnecessary power consumption has beenreduced by stopping clock oscillation, as represented by a HALT mode ofthe microcomputer, while with development of recent super-micromachiningand high-degree integration technique, it has becomes impossible toneglect influences of a static power supply current that flows in asteady state, which is exerted on the power consumption.

In cases where plural function blocks are integrated on onesemiconductor, even when it is possible to stop supply of power to eachof the function blocks, the power consumption of the signal processingcircuit and the microcomputer is increased when these units aremanufactured by the same process, because characteristics which arenecessary in the respective manufacturing processes are different fromeach other. For example, when they are manufactures by the Low-Vtprocess to reduce the power consumption during the operation, theleakage current in the microcomputer which is constantly supplied withpower, i.e., the leakage current of the first function block 11 becomeslarge. When the High-Vt process is employed to reduce this leakagecurrent, it becomes impossible to lower the operating voltage, wherebythe current consumption during the operation is increased.

The present invention is made to solve the above-mentioned problem, andhas for its object to provide a multiple power source semiconductorintegrated circuit in which function blocks for performing signalprocessing and a microcomputer are integrated, thereby enabling to stopsupply of power to a function block which is not used, to reduceunnecessary power consumption.

DISCLOSURE OF THE INVENTION

To solve the above-mentioned problem, according to claim 1 of thepresent invention, there is provided a multiple power sourcesemiconductor integrated circuit including: plural function blocks thatare supplied with power from different power supply circuits,respectively; a microcomputer for controlling the supply of power to theplural function blocks, the microcomputer being one of the pluralfunction blocks; and a power supply control circuit for controlling thesupply of power by the power supply circuits under the control of themicrocomputer.

According to claim 2 of the present invention, in the multiple powersource semiconductor integrated circuit of claim 1, the power supplycontrol circuit stops the supply of power to the microcomputer by thepower supply circuit when receiving predetermined data from themicrocomputer, and restarts the supply of power to the microcomputer bythe power supply circuit when receiving an interrupt signal fromoutside.

According to claim 3 of the present invention, in the multiple powersource semiconductor integrated circuit of claim 1 or 2, the powersupply control circuit includes a register for storing the interruptsignal, and the microcomputer detects contents of the interrupt signalthat is stored in the register, after restart of the supply of power.

According to claim 4 of the present invention, in the multiple powersource semiconductor integrated circuit of any of claims 1 to 3, thepower supply control circuit outputs a power cutoff signal to the powersupply circuits when the supply of power by the plural power supplycircuits is to be halted, and the function blocks and the power supplycontrol circuit each include an inter-block signal fixing circuit forfixing an input logic from a circuit that is in a state where the supplyof power is halted, at “L” or “H” level in accordance with the powercutoff signal.

According to claim 5 of the present invention, in the multiple powersource semiconductor integrated circuit of any of claims 1 to 4, thepower supply control circuit outputs a power cutoff signal to the powersupply circuits when the supply of power by the plural power supplycircuits is to be stopped, and the function blocks and the power supplycontrol circuit each include an inter-block signal fixing circuit forfixing an output logic to a circuit to which supply of power is halted,at “L” level in accordance with the power cutoff signal.

According to claim 6 of the present invention, the multiple power sourcesemiconductor integrated circuit of any of claims 1 to 5 includes: astorage means which is always supplied with power and retains systeminformation while the supply of power to the respective function blocksis halted.

According to claim 7 of the present invention, the multiple power sourcesemiconductor integrated circuit of any of claims 1 to 6 includes: aninput/output terminal circuit for giving and receiving a signal to/fromoutside, and the power supply control circuit and the input/outputterminal operate on power that is supplied from a common power supplycircuit.

According to claim 8 of the present invention, in the multiple powersource semiconductor integrated circuit of any of claims 1 to 6, thepower supply control circuit operates on power that is supplied to theplural power supply circuits, and outputs an all power cutoff signal forstopping the supply of power by all of the plural power supply circuits.

As described above, according to claim 1 of the present invention, thereis provided a multiple power source semiconductor integrated circuitincluding: plural function blocks that are supplied with power fromdifferent power supply circuits, respectively; a microcomputer forcontrolling the supply of power to the plural function blocks, themicrocomputer being one of the plural function blocks; and a powersupply control circuit for controlling the supply of power by the powersupply circuits under the control of the microcomputer. Therefore, theplural power supply circuits are controlled by the microcomputer via thepower supply control circuit, whereby it is possible to perform controlof supply of power to the respective function blocks as required whileperforming a system operation, and reduce unnecessary power consumption.

According to claim 2 of the present invention, in the multiple powersource semiconductor integrated circuit of claim 1, the power supplycontrol circuit stops the supply of power to the microcomputer by thepower supply circuit when receiving predetermined data from themicrocomputer, and restarts the supply of power to the microcomputer bythe power supply circuit when receiving an interrupt signal fromoutside. Therefore, the plural power supply circuits are controlled bythe microcomputer via the power supply control circuit, whereby it ispossible to perform control of supply of power to the microcomputer, andreduce unnecessary power consumption.

According to claim 3 of the present invention, in the multiple powersource semiconductor integrated circuit of claim 1 or 2, the powersupply control circuit includes a register for storing the interruptsignal, and the microcomputer detects contents of the interrupt signalthat is stored in the register, after restart of the supply of power.Therefore, the microcomputer can check the state of the system when thesupply of power is restarted.

According to claim 4 of the present invention, in the multiple powersource semiconductor integrated circuit of any of claims 1 to 3, thepower supply control circuit outputs a power cutoff signal to the powersupply circuits when the supply of power by the plural power supplycircuits is to be halted, and the function blocks and the power supplycontrol circuit each include an inter-block signal fixing circuit forfixing an input logic from a circuit that is in a state where the supplyof power is halted, at “L” or “H” level in accordance with the powercutoff signal. Therefore, it is possible to prevent a current fromflowing through a circuit on a receiving end by a signal of anintermediate voltage, which is outputted from a circuit to which supplyof power is halted, thereby reducing unnecessary power consumption.

According to claim 5 of the present invention, in the multiple powersource semiconductor integrated circuit of any of claims 1 to 4, thepower supply control circuit outputs a power cutoff signal to the powersupply circuits when the supply of power by the plural power supplycircuits is to be stopped, and the function blocks and the power supplycontrol circuit each include an inter-block signal fixing circuit forfixing an output logic to a circuit to which supply of power is halted,at “L” level in accordance with the power cutoff signal. Therefore, byfixing a signal that is outputted to a circuit to which supply of poweris halted at “L” level, it is possible to prevent characteristicsdeterioration of a P-channel transistor in a circuit on a receiving end.

According to claim 6 of the present invention, the multiple power sourcesemiconductor integrated circuit of any of claims 1 to 5 includes: astorage means which is always supplied with power and retains systeminformation while the supply of power to the respective function blocksis halted. Therefore, by storing information of a state immediatelybefore halting the supply of power to the microcomputer in the storagecircuit and reading the stored information at restarting the supply ofpower, it is possible to restart processings from the state immediatelybefore halting the supply of power.

According to claim 7 of the present invention, the multiple power sourcesemiconductor integrated circuit of any of claims 1 to 6 includes: aninput/output terminal circuit for giving and receiving a signal to/fromoutside, and the power supply control circuit and the input/outputterminal operate on power that is supplied from a common power supplycircuit. Therefore, even in a state after the microcomputer is poweredoff, it is possible to keep the state of the input/output terminalcircuit.

According to claim 8 of the present invention, in the multiple powersource semiconductor integrated circuit of any of claims 1 to 6, thepower supply control circuit operates on power that is supplied to theplural power supply circuits, and outputs an all power cutoff signal forstopping the supply of power by all of the plural power supply circuits.Therefore, it is possible to eliminate power which is consumed by thepower supply circuits in the standby state.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram illustrating structures of a multiple powersource semiconductor integrated circuit according to a first embodimentof the present invention, and power supply circuits for the multiplepower source semiconductor integrated circuit.

FIG. 2 is a diagram for explaining a relationship between power supplycontrol and states of power supply in the multiple power sourcesemiconductor integrated circuit according to the first embodiment.

FIG. 3 is a block diagram illustrating structures of a multiple powersource semiconductor integrated circuit according to a second embodimentof the present invention, and power supply circuits for the multiplepower source semiconductor integrated circuit.

FIG. 4 is a block diagram illustrating structures of a principal part ofa multiple power source semiconductor integrated circuit according to athird embodiment of the present invention, and power supply circuits forthe multiple power source semiconductor integrated circuit.

FIG. 5 is a diagram for explaining functions of the multiple powersource semiconductor integrated circuit according to the thirdembodiment.

FIG. 6 is a block diagram illustrating structures of a principal part ofa multiple power source semiconductor integrated circuit according to afourth embodiment of the present invention, and power supply circuitsfor the multiple power source semiconductor integrated circuit.

FIG. 7 is a diagram for explaining functions of the multiple powersource semiconductor integrated circuit according to the fourthembodiment.

FIG. 8 is a block diagram illustrating structures of a multiple powersource semiconductor integrated circuit according to a fifth embodimentof the present invention, and power supply circuits for the multiplepower source semiconductor integrated circuit.

FIG. 9 is a block diagram illustrating structures of a principal part ofa multiple power source semiconductor integrated circuit according to asixth embodiment of the present invention, and power supply circuits forthe multiple power source semiconductor integrated circuit.

FIG. 10 is a flowchart showing a procedure of an operation of themultiple power source semiconductor integrated circuit according to thesixth embodiment, in a case where the power supply is halted.

FIG. 11 is a flowchart showing a procedure of an operation of themultiple power source semiconductor integrated circuit according to thesixth embodiment, in a case where the power supply is started.

FIG. 12 is a block diagram illustrating structures of a multiple powersource semiconductor integrated circuit according to a seventhembodiment of the present invention, and power supply circuits for themultiple power source semiconductor integrated circuit.

FIG. 13 is a block diagram illustrating structures of a conventionalmultiple power source semiconductor integrated circuit and power supplycircuits for the multiple power source semiconductor integrated circuit.

BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, embodiments of the present invention will be described withreference the drawings. FIGS. 1 to 12 are diagrams for explainingmultiple power source semiconductor integrated circuits according tothese embodiments. In these figures, the same or correspondingcomponents are denoted by the same references, and their descriptionswill not be repeated.

(Embodiment 1)

Initially, an example corresponding to a multiple power sourcesemiconductor integrated circuit as defined in claims 1 and 2 of thepresent invention will be described as a first embodiment, withreference to FIGS. 1 and 2.

FIG. 1 is a block diagram illustrating structures of a multiple powersource semiconductor integrated circuit according to the firstembodiment, and power supply circuits for the multiple power sourcesemiconductor integrated circuit.

In FIG. 1, reference numeral 1 denotes a multiple power sourcesemiconductor integrated circuit, numeral 2 denotes a main power source,and numerals 3 to 7 denote first to fifth power supply circuits thattransform a power supply voltage from the main power source 2 intoarbitrary power supply voltages VDD1 to VDD5, and supply these voltagesto the multiple power source semiconductor integrated circuit. Numerals11 to 14 denote first to fourth function blocks that are included in themultiple power source semiconductor integrated circuit 1, numeral 15denotes an input/output terminal circuit that gives/receives a signalto/from an external device of the multiple power source semiconductorintegrated circuit 1, numerals 21 to 25 denote first to fifth externalpower supply terminals for supplying the power supply voltages VDD1 toVDD5 to the multiple power source semiconductor integrated circuit 1,numerals 31 to 35 denote first to fifth internal power supply lines,numeral 40 denote a power supply control circuit for controlling supplyof power to the respective function blocks 11 to 14, numerals 41 to 44denote first to fourth power cutoff signals that are outputted from thepower supply control circuit 40 to control supply of power by the firstto fourth power supply circuits 3 to 6 and halt of the supply of power,numerals 45 to 48 denote first to fourth external output terminals foroutputting the power cutoff signals 41 to 44 from the multiple powersource semiconductor integrated circuit 1, numeral 51 denotes an RSlatch circuit that holds the power cutoff signals, and numeral 52denotes a three-input OR circuit that generates a reset signal for theRS latch circuit 51. Numeral 53 denotes a control signal for instructinghalt of the supply of power, numeral 54 denotes a reset signal forinitializing the multiple power source semiconductor integrated circuit1, numerals 55 and 56 denote interrupt signals which are generated bykey operation or the like, for starting the supply of power, andnumerals 57 to 59 denote external input terminals.

The power supply control circuit 40 includes the RS latch circuit 51that holds the power cutoff signals, and the three-input OR circuit 52for restarting the supply of power. In the RS latch circuit 51, thefirst power cutoff signal 41 is connected to the Q node (output node),the control signal 53 from the first function block 11 (microcomputer)is connected to the S node (set node), and an output from thethree-input OR circuit 52 is connected to the R-node (reset node). Thereset signal 54 from the external input terminal 57 is connected to thefirst input of the three-input OR circuit, the interrupt signal 55 fromthe external input terminal 58 is connected to the second input, and theinterrupt signal 56 from the external input terminal 59 is connected tothe third input.

This FIG. 1 shows the example in which the first function block 11 is amicrocomputer for controlling the system, the second function block 12is a signal processing circuit, the third function block 13 is anearthquake-resistant storage circuit, and the fourth function block 14is an analog circuit. However, the present invention does not limit thefunctions of the function blocks included in the multiple power sourcesemiconductor integrated circuit 1, and the number of the functionblocks. The second to fourth function blocks 12 to 14 can be signalprocessing circuits that implement characteristic functions of thisdevice. Further, the multiple power source semiconductor integratedcircuit 1 may include an arbitrary number of function blocksrespectively having arbitrary functions.

Further, two interrupt signals, i.e., the first and the second interruptsignals 55 and 56 are provided to restart the supply of power, while thenumber of the interrupt signals can be one or more.

Next, the operation of the multiple power source semiconductorintegrated circuit 1 that is constructed as described above will bedescribed.

When the main power source 2 is turned on, the fifth power supplycircuit 7 transforms a power supply voltage that is supplied. from themain power 2 into an arbitrary power supply voltage VDD5, and suppliesthe same to the multiple power source semiconductor integrated circuit1. The first power supply circuit 3 transforms the power supply voltagethat is supplied from the main power 2 into a power supply voltage VDD1,and supplies the same in accordance with the power cutoff signal 41 thatis outputted from the multiple power source semiconductor integratedcircuit 1. Similarly, the second power supply circuit 4 transforms thepower supply voltage that is supplied from the main power 2 into a powersupply voltage VDD2 and supplies the same in accordance with the powercutoff signal 42, the third power supply circuit 5 transforms the powersupply voltage that is supplied from the main power 2 into a powersupply voltage VDD3 and supplies the same in accordance with the powercutoff signal 43, and the fourth power supply circuit 6 transforms thepower supply voltage that is supplied from the main power 2 into a powersupply voltage VDD4 and supplies the same in accordance with the powercutoff signal 44. The multiple power source semiconductor integratedcircuit 1 receives the power supply voltage VDD1 that is supplied fromthe first. power supply circuit 3 through the first external powersupply terminal 21. Similarly, the multiple power source semiconductorintegrated circuit 1 receives the power supply voltage VDD2 that issupplied from the second power supply circuit 4 through the secondexternal power supply terminal 22, the power supply voltage VDD3 that issupplied from the third power supply circuit 5 through the thirdexternal power supply terminal 23, and the power supply voltage VDD4that is supplied from the fourth power supply circuit 6 through thefourth external power supply terminal 24, respectively.

The power supply that is received through the fifth external powersupply terminal 25 is supplied to the input terminal circuit 15 and thepower supply control circuit 40 via the fifth internal power supply line35, and the power supply that is received through the first externalpower supply terminal 21 is supplied to the first function block 11 viathe first internal power supply line 31. Similarly, the power supplythat is received through the second external power supply terminal 22 issupplied to the second function block 12 via the second internal powersupply line 32, the power supply that is received through the thirdexternal power supply terminal 23 is supplied to the third functionblock 13 via the third internal power supply line 33, and the powersupply that is received through the fourth external power supplyterminal 24 is supplied to the fourth function block 14 via the fourthinternal power supply line 34, respectively.

The power supply control circuit 40 halts supply of power in accordancewith a control signal 53 that is outputted from the first. functionblock 11 (microcomputer) which controls the entire system. The operationof the power supply control circuit 40 will be described in detail withreference to a figure.

FIG. 2 is a diagram for explaining states of the control signal 53, thereset signal 54, the first interrupt signal 55, and the second interruptsignal 56, and states of the supply of power to the first function block11. In FIG. 2, the horizontal axis indicates the lapse of time fromperiod (a) to period (f). With respect to the state of supply of powerto the first function block, “1” indicates a state where the power isbeing supplied, while “0” indicates a state where the supply of powersupply is halted. The first power supply circuit 3 halts the supply ofpower when the first power cutoff signal 41 is at “H” level whilesupplying the power when the signal 41 is at “L” level.

When the reset signal 54 is in a reset state (at “H” level) (period(a)), the RS latch circuit 51 is set at “L” level, and thereaftercontinuously holds the “L” level regardless of the level of the resetsignal 54. Accordingly, the first power cutoff signal 41 becomes “L”level, and then the first power supply circuit 3 starts the supply ofpower to the function block When the control signal 53 is at “H” level(periods (b), (d), or (f)), the RS latch circuit 51 is set at “H” level,and thereafter continuously holds the “H” level regardless of the levelof the control signal 53. Accordingly, the first power cutoff signal 41becomes “H” level, and then the first power supply circuit 3 stops thesupply of power to the function block 11.

When the first interrupt signal 55 is at “H” level (period (c)) or thesecond interrupt signal 56 is at “H” level (period (e)), the RS latchcircuit 51 is set at “L” level, and thereafter continuously holds the“L” level regardless of the level of the first interrupt signal 55.Accordingly, the first power cutoff signal 41 becomes “L” level, andthen the first power supply circuit 3 starts the supply of power to thefunction block 11.

As described above, the multiple power source semiconductor integratedcircuit 1 according to the first embodiment includes the first to fourthfunction blocks 11 to 14 which receive supply of power from thecorresponding first to fourth power supply circuits 3 to 6,respectively, and the power supply control circuit 40 which controls thesupply of power from the first to fourth power supply circuits 3 to 6 onthe basis of control by the microcomputer which is the first functionblock 11, in which the power supply control circuit 40 stops supply ofpower from the respective function blocks including the microcomputeritself when it received predetermined data from the first function block11, while restarting the supply of power when it received the firstinterrupt signal 55 or the second interrupt signal 56 from outside.Therefore, it is possible to perform the control of the supply of powerto the respective function blocks as required while performing thesystem operation, whereby it is possible to reduce unnecessary powerconsumption by stopping the supply of power to function blocks that arenot working. Accordingly, for example when the multiple power sourcesemiconductor integrated circuit 1 is mounted on a portable electronicdevice, it is possible to halt the supply of power to the respectivefunction blocks including the microcomputer that controls the systemwhen the portable electronic device is not used, and wait for the nextkey operation (interrupt control) (to be in a standby state), therebysuppressing the power consumption in the standby state.

(Embodiment 2)

An example corresponding to a multiple power source semiconductorintegrated circuit as defined in claim 3 of the present invention willbe described as a second embodiment, with reference to FIG. 3.

FIG. 3 is a block diagram illustrating structures of a multiple powersource semiconductor integrated circuit according to the secondembodiment, and power supply circuits for the multiple power sourcesemiconductor integrated circuit. In FIG. 3, the same or correspondingelements as those in FIG. 1 are denoted by the same references, andtheir detailed descriptions will not be given.

The multiple power source semiconductor device la according to thesecond embodiment includes a power supply control circuit 40 a that isprovided with a register 61 for holding data of the first interruptsignal (which is shown as a first power recover signal in FIG. 3) 55,and a register 62 for holding data of- the second interrupt signal(which is shown as a second power recover signal in FIG. 3) 56, and theregister 61 and the first function block 11 are connected by an internalsignal 63, and the register 62 and the first function block 11 areconnected by an internal signal 64, respectively.

Next, the operation of the multiple power source semiconductorintegrated circuit la that is constructed as described above will bedescribed.

When supply of power is restarted by the first interrupt signal 55 orthe second interrupt signal 56 while the supply of power to the first tofourth function blocks11 to 14 is halted (when the respective functionblocks are on standby), the registers 61 and 62 hold data of the firstand second interrupt signals 55 and 56, respectively. When the supply ofpower is restarted, the first function block 11 obtains the data thatare held in the internal registers 61 and 62 via the internal signal 63and 64, to check contents of the interrupt control.

As described above, according to the multiple power source semiconductorintegrated circuit la of the second embodiment, the register 61 forholding data of the interrupt signal 55 and the register 62 for holdingdata of the interrupt signal 56 are provided in the power supply controlcircuit 40 a, and the register 61 and the first function block 11 areconnected by the internal signal 63, and the register 62 and the firstfunction block 11 are connected by the internal signal 64, respectively.Therefore, when a standby state in-which the supply of power is haltedis released by some key operation (interrupt control) to restart thesupply of power to the first to fourth function blocks 11 to 14, thefirst function block 11 checks contents of the key operation by checkingthe data that are held in the register 61 or 62, thereby executing apredetermined operation in accordance with the key operation.

(Embodiment 3)

An example corresponding to a multiple power source semiconductorintegrated circuit as defined in claim 4 will be described as a thirdembodiment, with reference to FIGS. 4 and 5.

FIG. 4 is a block diagram illustrating structures of a principal part ofa multiple power source semiconductor integrated circuit 1 b accordingto the third embodiment, and power supply circuits for the multiplepower source semiconductor integrated circuit lb. In FIGS. 4 and 5, thesame or corresponding components as those in FIG. 1 are denoted by thesame reference-numerals, and their detailed descriptions will beomitted.

In a multiple power source semiconductor device 1 b according to thethird embodiment, the second function block 12 includes a CMOS invertercircuit 74 for generating a inter-block signal 72, and the firstfunction block 11 includes a two-input OR circuit 71 that outputs an ORbetween the power cutoff signal 42 and the inter-block signal 72 that isoutputted from the second function block 12 as the internal signal 73,to fix the inter-block signal 72 from the second function block 12 whensupply of power to the second function block 12 is stopped.

The two-input OR circuit 71 that is provided in the first function block11 is constituted by first to third p-MOS transistors TP11 to TP13, andfirst to third n-MOS transistor TN11 to TN13. Gate electrodes of thefirst p-MOS transistor TP11 and the first n-MOS transistor TN11 areconnected with each other, thereby constituting an input terminal forreceiving the inter-block signal 72. Gate electrodes of the second p-MOStransistor TP12 and the second n-MOS transistor TN12 are connected witheach other, thereby constituting an input terminal for receiving thepower cutoff signal 42. The drain electrode of the first p-MOStransistor TP11 and the drain electrodes of the first and second n-MOStransistors TN11 and TN12 are connected to the gate electrodes of thethird p-MOS transistor TP13 and the third n-MOS transistor TN13,respectively. The source electrode of the first p-MOS transistor TP11 isconnected to the drain electrode of the second p-MOS transistor TP12,and the source electrode of the second p-MOS transistor TP12 isconnected to a first internal power supply line 31, thereby beingsupplied with the power supply voltage VDD1. The source electrodes ofthe first and second n-MOS transistors TN11 and TN12 are connected tothe ground line GND. The source electrode of the third p-MOS transistorTP13 are connected to the first internal power supply line 31, therebybeing supplied with the power supply voltage VDD1. The source electrodeof the third n-MOS transistor TN13 is connected to the ground line GND.The. drain electrode of the third p-MOS transistor TP13 and the drainelectrode of the third n-MOS transistor TN13 constitute an outputterminal for supplying the internal signal 73 to the first functionblock 11.

The CMOS inverter circuit 74 that included in the second function block12 is constituted by a fourth p-MOS transistor TP14 and a fourth n-MOStransistor TN14, and its output is connected to the inter-block signal72. Gate electrodes of the fourth p-MOS transistor TP14 and the fourthn-MOS transistor TN14 are connected with each other, therebyconstituting an input terminal for receiving an input. The sourceelectrode of the fourth p-MOS transistor TP14 is connected to the secondinternal power supply line 32, thereby being supplied with the powersupply voltage VDD2. The source electrode of the fourth n-MOS transistorTN14 is connected to the ground line GND. The drain electrode of thefourth p-MOS transistor TP14 and the drain electrode of the fourth n-MOStransistor TN14 are connected with each other, thereby constituting anoutput terminal for supplying the inter-block signal 72.

Next, the operation of the multiple power source semiconductorintegrated circuit 1 b that is constructed as described above while thesupply of power is halted will be described.

FIG. 5 is a diagram showing an operation in a case where the powercutoff signal 42 is fixed at “H” level, to halt the supply of power tothe second function block 12.

In this case, the supply of power to the inverter circuit 74 that isincluded in the second function block 12 is cut off, whereby the circuit74 outputs an inconstant level (intermediate level) according to theremaining charge of the second internal power supply line 32. Further,the second p-MOS transistor TP12 that constitutes the two-input ORcircuit is included in the first function 11 is turned OFF. Accordingly,the supply of power to the first p-MOS transistor TP11 is cut off,thereby avoiding transmission of an inconstant logic (intermediatepotential) via the input signal 72. Further, “L” level is supplied tothe respective gate electrodes of the third p-MOS transistor TP13 andthe third n-MOS transistor TN13 by turning ON the second n-MOStransistor TN12, whereby the third p-MOS transistor turns in an ONstate, the third n-MOS transistor turns in an OFF state, and then theoutput signal is fixed at a “H” level.

As described above, according to the multiple power source semiconductorintegrated circuit 1 b of the third embodiment, when the supply of powerto the second function block 12 is halted in accordance with the powercutoff signal 42, the input logic from the second function block 12 tothe first function block 11 is fixed at “H” level. Therefore, while thesupply of power to the second function block 12 is halted, it ispossible to avoid transmission of the inconstant logic from the secondfunction block 12 and generation of a flow-through current due to inputof the intermediate potential to the gate electrode.

The third embodiment describes the example where the second functionblock 12 is provided with the CMOS inverter circuit 74, and the firstfunction block 11 is provided with the two-input OR circuit 71. However,it is also possible to provide a CMOS inverter circuit for generating aninternal signal at respective output stages of the first to fourthfunction blocks 11 to 14, the input/output terminal circuit 15, and thepower supply control circuit 40, and a two-input OR circuit that outputsan OR between the power cutoff signal and an inter-block signal from afunction block of the next stage as an internal signal, at their inputstages. Accordingly, in the first to fourth function blocks 11 to 14,the input/output terminal circuit 15 and the power supply controlcircuit 40, when supply of power to a function block that is connectedin the following stage is halted, it is possible to avoid transmissionof an inconstant logic from the following function block and generationof a flow-through current due to input of an intermediate potential tothe gate electrode.

(Embodiment 4)

An example corresponding to a multiple power source semiconductorintegrated circuit as defined in claim 5 of the present invention willbe described as a fourth embodiment, with reference to FIGS. 6 and 7.

FIG. 6 is a block diagram illustrating structures of a principal part ofa multiple power source semiconductor integrated circuit 1 c accordingto the fourth embodiment, and power supply circuits for the multiplepower source semiconductor integrated circuit 1 c. In FIGS. 6 and 7, thesame or corresponding components as those in FIG. 4 are denoted by thesame references, and their detailed descriptions will be omitted.

In the multiple power source semiconductor device 1 c according to thefourth embodiment, the first function block 11 includes a first invertercircuit 81, and a two-input NOR circuit 82 that outputs a NOR between anoutput from the first inverter circuit 81 and a power cutoff signal 42as an inter-block signal 84, to fix the inter-block signal 84 to thesecond function block 12 at “L” level when power supply to the secondfunction block 12 is halted, and the second function block 12 includes asecond inverter circuit 86 to which the inter-block signal 84 from thefirst function block 11 is inputted.

The input node of the first inverter circuit 81 that is provided in thefirst function block 11 is connected to an internal signal 83, and theoutput node thereof is connected to a second input of the two-input NORcircuit 82. The first inverter circuit is constituted by a first p-MOStransistor TP21 and a first n-MOS transistor TN21. Gate electrodes ofthe first p-MOS transistor TP21 and the first n-MOS transistor TN21 areconnected with each other, thereby constituting an input terminal forreceiving the internal signal 83. The source electrode of the firstp-MOS transistor TP21 is connected to the first internal power supplyline 31, thereby being supplied with the power supply voltage VDD1. Thesource electrode of the first n-MOS transistor TN21 is connected to theground line GND. The drain electrode of the first p-MOS transistor TP21and the drain electrode of the first n-MOS transistor TN21 are connectedwith each other, thereby being connected to a first input of thetwo-input NOR circuit 82. Further, the second input of the two-input NORcircuit 82 is connected to the power cutoff signal 42, and the outputthereof is connected to the inter-block signal 84, respectively. Thetwo-input NOR circuit 82 is constituted by second and third p-MOStransistors TP22 and TP23, and second and third n-MOS transistors TN22and TN23. The respective gate electrodes of the second p-MOS transistorTP22 and the second n-MOS transistor TN22 are connected with each other,thereby constituting an input terminal for receiving the output from thefirst inverter circuit 81. The respective gate electrodes of the thirdp-MOS transistor TP23 and the third n-MOS transistor TN23 are connectedwith each other, thereby constituting an input terminal for receivingthe power cutoff signal 42. The drain electrode of the second p-MOStransistor TP22 and the drain electrodes of the second and third n-MOStransistors TN22 and TN23 constitute an output terminal for outputtingthe inter-block signal 84. The source electrode of the second p-MOStransistor TP22 is connected to the drain electrode of the third p-MOStransistor TP23, and the source electrode of the third p-MOS transistorTP23 is connected to the first internal power supply line 31, therebybeing supplied with the power supply voltage VDD1. The source electrodesof the first and second n-MOS transistors TN22 and TN23 are connected tothe ground line GND.

The input of the second inverter circuit 86 that is provided in thesecond function block 12 is connected to the inter-block signal 84. Thissecond inverter circuit is constituted by a fourth p-MOS transistor TP24and a fourth N-MOS transistor TN24. The respective gate electrodes ofthe fourth p-MOS transistor TP24 and the fourth n-MOS transistor TN24are connected with each other, thereby constituting an input terminalfor receiving an output signal from the two-input NOR circuit 82. Thesource electrode of the first p-MOS transistor TP24 is connected to thepower voltage VDD2, and the source electrode of the first n-MOStransistor TN24 is connected to the ground lien GND. The drain electrodeof the first p-MOS transistor TP24 and the drain electrode of the firstn-MOS transistor TN24 are connected with each other, therebyconstituting an output terminal.

Next, the operation of the multiple power source semiconductorintegrated circuit 1 c that is constructed as described above, while thesupply of power is halted, will be described.

FIG. 7 is a diagram showing an operation in a case where the powercutoff signal 42 is fixed at “H” level and the supply of power to thesecond function block 12 is halted.

In this case, the third p-MOS transistor TP23 in the two-input NORcircuit 82 that is included in the first function block 11 turns in anOFF state, and the third n-MOS transistor TN23 turns in an ON state.

As described above, according to the multiple power source semiconductorintegrated circuit 1 c of the fourth embodiment, when the supply ofpower to the second function block 12 is halted in accordance with thepower cutoff signal 42, the inter-block signal 84 for the secondfunction block 12 is fixed at “L” level. Therefore, a “L” level signalis supplied to the second inverter circuit that is included in thesecond function block 12 while the supply of power is halted, whereby itis possible to avoid deterioration in the characteristics of the p-MOStransistor due to application of a “H” level voltage for a long time tothe gate electrode of the p-MOS transistor in a state where the supplyof power is halted.

This fourth embodiment describes an example where the first invertercircuit 81 and the two-input NOR circuit 82 are provided in the firstfunction block 11, and the second invertercircuit86isprovidedinthesecondfunctionblock12. However, it is alsopossible that an inverter circuit and a two-input NOR circuit thatoutputs a NOR between an output from the inverter circuit and the powercutoff signal as an inter-block signal are provided at respective outputstages of the first to fourth function blocks 11 to 14, the input/outputterminal 15 and the power supply control circuit 40, and an invertercircuit to which the inter-block signal from a function block that isconnected in the preceding stage is inputted, is provided at respectiveinput stages thereof. Accordingly, when the supply of power to the firstto fourth function blocks 11 to 14, the input/output terminal circuit15, and the power supply control circuit 40 are halted, a “L” levelsignal is supplied to a function block that is connected in thefollowing stage, whereby it is possible to avoid deterioration in thecharacteristics of the p-MOS transistor due to application of a “H”level voltage for a long time to the gate electrode of the p-MOStransistor which is in a state where the supply of power is halted.

(Embodiment 5)

An example corresponding to a multiple power source semiconductorintegrated circuit as defined in claim 6 of the present invention willbe described as a fifth embodiment, with reference to FIG. 8.

FIG. 8 is a block diagram illustrating structures of a multiple powersource semiconductor integrated circuit 1 d according to the fifthembodiment, and power supply circuits for the multiple power sourcesemiconductor integrated circuit 1 d. In FIG. 8, the same orcorresponding components as those in FIG. 1 are denoted by the samereferences, and their detailed descriptions will not be given.

In the multiple power source semiconductor integrated circuit Idaccording to the fifth embodiment, a power supply control circuit 40 dis constantly supplied with power, and a storage circuit 90 that iscapable of recording or reading data from the first function block 11via a signal group 91 is provided in the power supply control circuit 40d.

Here, the first function block 11 is a microcomputer for controlling thesystem, and is designed to record data that are required for the systemoperation (key operation, display setting, setting of volumes, or thelike) into the storage circuit 90 via the signal group 91 before haltingthe supply of power, and read the data that are stored in the storagecircuit 90 immediately after restarting the supply of power.

Next, the operation of the multiple power source semiconductorintegrated circuit Id that is constructed as described above will bedescribed.

The supply of power to the respective function blocks 11 to 14 areperformed in the same manner as described in any of the first to thirdembodiments. Before stopping the power supply to itself, the firstfunction block 11 records data of the system operation (key operation,display setting, setting of volumes or the like) into the storagecircuit 90 of a state where the power is constantly supplied, and thenhalts the supply of power. Since the storage circuit 90 is constantlysupplied with power even when the supply of power to the all functionblocks 11 to 14 is halted, the data that are recorded in the storagecircuit 90 immediately before the supply of power are not lost and held.The first function block 11 reads the data that are held in the storagecircuit 90 immediately after restart of the supply of power, andrestarts the processing from the previous state before the halt of thesupply of power.

As described above, according to the multiple power source semiconductorintegrated circuit 1 d of the fifth embodiment, the power supply controlcircuit 40 d is controlled to be constantly supplied with power, and isprovided with the storage circuit 90, for which data are recorded orread by the first function block 11, and data which are required for thesystem operation are recorded in the storage circuit 90 before haltingthe supply of power, and are held while the supply of power is halted,whereby it is possible to eliminate the need of repeating the settingwhich has been performed before halting the supply of power, by readingthe stored data after restart of the supply of power.

(Embodiment 6)

According to the aforementioned multiple power source semiconductorintegrated circuit of any of the first to fifth embodiment, the powersupply control circuit 40 and the input/output terminal circuit 15employ the same power source, for example as shown in FIG. 1. This isquite important in implementing the same function as in the case wherethe signal processing circuit and the microcomputer are provided onseparate semiconductor integrated circuits, in the multiple power sourcesemiconductor integrated circuit of any of these. embodiment. Theconventional microcomputer has a function of constantly performingcontrol of peripheral circuits at the same time of receiving a controlsignal from outside in a state where the power is constantly supplied.On integrating such microcomputer, when power is constantly suppliedalso to the input/output terminal circuit that controls the peripheralcircuits, at least the state of the input/output terminal (inputting, Hlevel outputting, L level outputting) can be maintained, therebypreventing malfunctions of electronic devices due to instability of acontrol signal for the peripheral circuits.

Hereinafter, an example corresponding to a multiple power sourcesemiconductor integrated circuit as defined in claim 7 of the presentinvention will be described as a sixth embodiment, with reference toFIGS. 9 to 11.

FIG. 9 is a block diagram illustrating structure of a principal part ofa multiple power source semiconductor integrated circuit 1 e accordingto the sixth embodiment, and power supply circuits for the multiplepower source semiconductor integrated circuit 1 e. In FIG. 9, the sameor corresponding components as those in FIG. 2 are denoted by the samereferences, and their detailed descriptions will be omitted.

In the multiple power source semiconductor integrated circuit 1 eaccording to the sixth embodiment, an input/output terminal circuit 15 ehas an input terminal 100 for receiving an external signal, a firstoutput terminal 101 for outputting “H” level when a power source 21 forthe first function block 11 is cut, and a second output terminal 102 foroutputting “L” level when the power source 21 for the first functionblock 11 is cut. For the sake of simplicity, it is assumed in thefollowing description that one input terminal 11, one first outputterminal 101, and one second output terminal 102 are provided, while thenumber of any of these terminals maybe zero, or two or more.

An output 103 of the input terminal 100, an input 104 of the firstoutput terminal 101, and an input 105 of the second output terminal 102are respectively connected to the first function block 11 which is amicrocomputer for controlling the system. Further, switching circuits107 to 109 to which a terminal hold signal 106 that is outputted fromthe power supply control circuit 40 is inputted, to switch signal levelsin accordance with the inputted terminal hold signal 106 are provided inthe terminals, respectively.

In addition, while not shown in detailed in the figure, the power supplycontrol circuit 40 e is designed like the power supply control circuit40 a according to the second embodiment so that when the first interruptsignal 55 or the second interrupt signal 56 becomes “H” level, a firstpower supply cutoff signal 41 that is outputted from the RS latchcircuit 51 becomes “L” level, thereby starting supply of power.

Further, the input/output terminal circuit 15 e and the power supplycontrol circuit 40 e are supplied with the power supply voltage VDD5that is obtained by transforming the main power 2 by means of the fifthpower supply circuit 7.

Next, the operation of the multiple power source semiconductorintegrated circuit 1 e that is constructed as described above will bedescribed.

Initially, an operation procedure which is performed by the multiplepower source semiconductor integrated circuit 1 e when halting supply ofpower to the first function block 11 will be described with reference toa flowchart of FIG. 10.

In halting the supply of power to the first function block 11, the firstfunction block 11 sets an input (a signal that is outputted from thefirst function block to the first output terminal) 104 to the firstoutput terminal 101 at “H” level (STEP 111). Next, the function block 11sets an input (a signal that is outputted from the first function blockto the second output terminal) 105 to the second output terminal 102 at“L” level (STEP 112). Next, the terminal hold signal 106 is set at “H”level (STEP 113).

When the terminal hold signal 106 becomes “H” level, the input terminal100 switches the switching circuit 107 to fix the output 103 at “L”level. Further, the first output terminal 101 and the second outputterminal 102 switch the switching circuits 108 and 109, to fix levels ofsignals that are externally outputted at “H” level and “L” level,respectively. By this operation, the input terminal 100, the firstoutput terminal 101, and the second output terminal 102 are isolatedfrom the control that is performed by the first function block 11 whilethe state in which the first function block 11 is operating ismaintained. Subsequently, the first function block 11 sets the powercutoff signal 41 at “H” level, to halt the supply of power to the firstfunction block 11 (STEP 114).

Next, the operation procedure in starting the supply of power to thesecond function block 12 will be described with reference to a flowchartof FIG. 11.

The supply of power is started by setting the first interrupt signal 55or the second interrupt signal 56 (not shown in FIG. 9) at “H” level asdescribed in the second embodiment (STEP 121). When the first interruptsignal 55 or the second interrupt signal 56 becomes “H” level, the firstpower cutoff signal 41 that is outputted from the RS latch circuit 51becomes “L” level. Thereby, the first power supply circuit 3 starts thesupply of power to the first function block 11 (STEP 122).

When supplied with power, the first function block 11 sets the input 104of the first output terminal 101 at “H” level (STEP 123), and sets theinput 105 of the second output terminal 102 at “L” level (STEP 124).Next, by setting the terminal hold signal 106 at “L” level, the outputof the first function block 11 is outputted to the first output terminal101 and the second output terminal 102 (STEP 125).

As described above, in the multiple power source semiconductorintegrated circuit 1 e according to the sixth embodiment, theinput/output terminal circuit 15 e includes the input. terminal 100 forreceiving an external signal, the first output terminal 101 foroutputting “H” level when the power source 21 of the function block 11is cut off, and the second output terminal 102 for outputting “L” levelwhen the power source 21 of the function block 11 is cut off. Therefore,even in cases where the first function block 11 as a microcomputer forcontrolling the system controls external circuits, it is possible tohalt supply of power to the first function block 11 and restart thesupply of power, without exerting any influence upon the externalcircuits.

(Embodiment 7)

An example corresponding to a multiple power source semiconductorintegrated circuit as defined in claim 8 of the present invention willbe described as a seventh embodiment, with reference to FIG. 12.

In many cases, batteries are employed as the main power for a portableelectronic device. For example, when the multiple power sourcesemiconductor integrated circuit le according to the sixth embodiment ismounted on a portable electronic device, it is important to reduce powerconsumption of the first to fifth power supply circuits 3 to 7 in viewof the entire power consumption of the portable electronic device. Thefifth power supply circuit 7 operates to constantly supply power, butsince the power efficiency of the DC/DC converter as a common powersupply circuit is about 80% to 90%, the corresponding power is consumed.Also in the first to fourth power supply circuits 3 to 7, because thepower is supplied to the power supply circuits themselves, leakagecurrents flow through the respective power supply circuits even when thesupply of power to the multiple power source semiconductor integratedcircuit 1 e is halted, resulting in battery consumption. An object ofthe seventh embodiment is to minimize such power consumption by thepower supply circuits.

FIG. 12 is a block diagram illustrating structures of a multiple powersource semiconductor integrated circuit if according to the seventhembodiment, and power supply circuits for the multiple power sourcesemiconductor integrated circuit 1 f. In FIG. 12, the same orcorresponding components as those in FIG. 1 are denoted by the samereferences, and their descriptions will not be given.

According to the multiple power source semiconductor integrated circuitif of the seventh embodiment, the power supply control circuit 40 foutputs a power cutoff signal 410 for controlling a main power cutoffcircuit 131 as a gate of supply of the main power 2 to the first tofifth power supply circuits 3 to 7, through a fifth output terminal 413,and directly receives power supply (a power supply voltage VDD6) fromthe main power 2 through a sixth external power supply terminal 130, andthe first to fourth function blocks 11 to 14 and the input/outputterminal circuit 15 are supplied with power by the power supply circuits3 to 7 that are controlled by the power supply control circuit 40 f. InFIG. 12, reference numeral 411 denotes a fifth power cutoff signal thatis outputted from the power supply control circuit 40 f for controllingsupply of power by the fifth power supply circuit 7 and halt of thesupply of power, and numeral 414 denotes a fifth external outputterminal for outputting the fifth power cutoff signal 411 from themultiple power source semiconductor integrated circuit 1 f.

The main power cutoff circuit 131 is constituted, for example, by an FET(Field Effect Transistor), and has a structure of stopping respectivesupply of power to the power supply circuits 3 to 7 in accordance with a“H” level output of the power cutoff signal 4 f.

In this seventh embodiment, the FET is used as the main power cutoffcircuit 131. However, any circuit such as a magnetic relay circuit canbe employed so long as it can cut off the power that is supplied to thefirst to fifth power supply circuits 3 to 7 in accordance with the powercutoff signal 410.

Next, the operation of the multiple power source semiconductorintegrated circuit 1 f that is constructed as described above whenhalting the supply of power will be described.

On halting the supply of power, the first function block 11 which is amicrocomputer for controlling the system instructs the power supplycontrol circuit 40 f to set the power cutoff signal 410 at “H” level.When the power cutoff signal 410 becomes “H” level, the main powercutoff circuit 131 halts the supply of power to the power supplycircuits 3 to 7.

As described above, according to the multiple power source semiconductorintegrated circuit if of the seventh embodiment, the power supplycontrol circuit 40 f is supplied with power directly from the main power2 via the sixth external power supply terminal 130, only theinput/output terminal circuit 15 is supplied with power from the fifthpower supply circuit 7, and then the power supply control circuit 40 foutputs the power cutoff signal 410 for controlling the main powercutoff circuit 131 as a gate for supply of the main power 2 to the firstto fifth power supply circuits 3 to 7 through the fifth output terminal413, as well as outputs the fifth power cutoff signal 411 forcontrolling supply of power and halt of the power supply by the fifthpower supply circuit 7 through the fifth external output terminal 414.Therefore, by halting supply of power to the first to fourth functionblocks 11 to 14. and the input/output terminal circuit 15, it ispossible to eliminate the power consumption by the power supply circuits3 to 7, thereby reducing consumption of the main power 2.

Here, it is desirable that the power supply control circuit 40 is anasynchronous structure which comprises the RS latch circuit 51 and thethree-input OR circuit 52. When the main power supply 2 is batteries andthe multiple power source semiconductor integrated circuit 1 f isoperated by the voltage of the batteries, variations in the voltagepresent problems. For example, when a nickel metal hydride secondarybattery is employed, the power supply voltage varies from about 1.5V to0.9V. While the operation of the semiconductor device becomes slowerwhen the voltage becomes lower, the RS latch circuit 51 and thethree-input OR circuit 52 forming an asynchronous structure can be madeperform an operation as the power supply control circuit 40 even whenthe battery voltage is lowered to such an extent that a synchronousdesign circuit operating in accordance with a reference clock which isgenerated does not operate.

INDUSTRIAL AVAILABILITY

A multiple power source semiconductor integrated circuit according tothe present invention in which a function block for performing signalprocessing and a microcomputer are integrated halts supply of power to afunction block that is not being used, thereby reducing unnecessarypower consumption. This circuit is useful because, for example, it ispossible to elongate an operating time per battery in a portableelectronic device that is driven by batteries.

1. A multiple power source semiconductor integrated circuit including:plural function blocks that are supplied with power from different powersupply circuits, respectively; a microcomputer for controlling thesupply of power to the plural function blocks, said microcomputer beingone of said plural function blocks; and a power supply control circuitfor controlling the supply of power by the power supply circuits underthe control of the microcomputer.
 2. The multiple power sourcesemiconductor integrated circuit as defined in claim 1 wherein the powersupply control circuit halts the supply of power to the microcomputer bythe power supply circuit when receiving predetermined data from themicrocomputer, and restarts the supply of power to the microcomputer bythe power supply circuit when receiving an interrupt signal fromoutside.
 3. The multiple power source semiconductor integrated circuitas defined in claim 1 wherein the power supply control circuit includesa register for storing the interrupt signal, and the microcomputerdetects contents of the interrupt signal that is stored in the register,after restart of the supply of power.
 4. The multiple power sourcesemiconductor integrated circuit as defined in claim 1 wherein the powersupply control circuit outputs a power cutoff signal to the power supplycircuits when the supply of power by the plural power supply circuits isto be halted, and the function blocks and the power supply controlcircuit each include an inter-block signal fixing circuit for fixing aninput logic from a circuit to which supply of power is halted, at “L” or“H” level in accordance with the power cutoff signal.
 5. The multiplepower source semiconductor integrated circuit as defined in claim 1wherein the power supply control circuit outputs a power cutoff signalto the power supply circuits when the supply of power by the pluralpower supply circuits is to be stopped, and the function blocks and thepower supply control circuit each include an inter-block signal fixingcircuit for fixing an output logic to a circuit that is in a state wherethe supply of power is halted, at “L” level in accordance with the powercutoff signal.
 6. The multiple power source semiconductor integratedcircuit as defined in claim 1 including: a storage means which is alwayssupplied with power and retains system information while the supply ofpower to the respective function blocks is halted.
 7. The multiple powersource semiconductor integrated circuit as defined in claim 1 including:an input/output terminal circuit for giving and receiving a signalto/from outside, and the power supply control circuit and theinput/output terminal operate on power that is supplied from a commonpower supply circuit.
 8. The multiple power source semiconductorintegrated circuit as defined in claim 1 wherein the power supplycontrol circuit operates on power that is supplied to the plural powersupply circuits, and outputs an all power cutoff signal for stopping thesupply of power by all of the plural power supply circuits.